Various abbreviations that appear in the specification and/or in the drawing figures are defined as follows:    ASIC application specific integrated circuit    DSP digital signal processor    MIMD multiple instruction stream multiple data stream    RF radio frequency    VLIW very long instruction word    FIR finite impulse response    CORDIC coordinate rotation digital calculation    I/O input/output    IU I/O unit    ALU arithmetic/logical unit    RB register block    CU communication unit    MU memory unit    EDGE enhanced data rates for global evolution    GSM global system for mobile communications    WCDMA wideband code division multiple access    UTRAN universal terrestrial radio access network    EUTRAN evolved UTRAN    UE user equipment    MIMO multiple input, multiple output
The computational requirements of a digital RF front end of some current and future multi-standard (multi-mode) mobile terminals are in the range of tens of billions of operations per second (GOPS) due at least in part to the number of functions that should be executed in parallel. A significant number of the data processing requirements arise from different FIR filter and CORDIC computations having different numbers of taps, different relative sampling frequencies, and different decimation settings. At present, there are no processor-based solutions available that would meet the extremely limited silicon area, and power consumption requirements, of an integrated circuit data processor platform. Further, and in general, existing approaches that utilize ASIC-based technology are not able to provide the flexibility, programmability and the fast time-to-market that is desired.
For example, the FIR is a commonly used type of digital filter, including adaptive digital filters, where digitized samples of a signal serve as inputs, and each filtered output is computed from a weighted sum of a finite number of previous inputs. A FIR filter can be designed to have linear phase (i.e., constant time delay, regardless of frequency).
Further by example, various types of CORDIC algorithms are described in an article “A survey of CORDIC algorithms for FPGA based computers”, R. Andraka, Copyright 1998 ACM 0-89791-978-5/98/01.
The problem has been traditionally approached through the use of dedicated ASIC blocks that implement the required functions (e.g., by providing dedicated FIR and/or CORDIC circuit blocks in the ASIC). However, the use of dedicated ASIC blocks does not provide flexibility, programmability or, typically, a fast time-to-market. While conventional DSP-based solutions might in theory address the foregoing problems, they generally require an excessive amount of silicon area and operating power.